鈥?/div>
Alternate frequency selections available through I
2
C
control.
Pin Configuration
*FS2//REF0
VDD
X1
X2
GND
GND
3V66-0
3V66-1
3V66-2
VDD
VDD
PCICLK_F
PCICLK0
GND
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDD
VDD
GND
GND
48MHz_0
48MHz_1
VDD
FS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
IOAPIC0
IOAPIC1
VDDL
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL
GND
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
GND
SDRAM_F
VDD
PD#
SCLK
SDATA
FS1
56-Pin 300mil SSOP
* This input has a 50K鈩?pull-down to GND.
Block Diagram
Functionality
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
/2
/3
REF0
FS2
X
X
FS1
0
0
1
1
1
1
FS0
0
1
0
1
0
1
ICS9250-27
Function
Tristate
Test
Active CPU = 66MHz
SDRAM = 100MHz
Active CPU = 100MHz
SDRAM = 100MHz
Active CPU = 133MHz
SDRAM = 133MHz
Active CPU = 133MHz
SDRAM = 100MHz
VDDL
CPU66/100/133 (2:0)
3
0
0
1
1
FS (2:0)
PD#
Control
Logic
3
8
3V66 (2:0)
SDRAM (7:0)
SDRAM_F
SDATA
SCLK
Config
Reg
/2
6
PCICLK (5:0)
PCICLK_F
/2
PLL2
2
IOAPIC (1:0)
VDDL
48MHz (1:0)
Power Groups
AVDD = Pin 22 Analog power for PLL
AGND = Pin 23 Analog ground
VDD48 = Pin 27 Analog power for 48MHz PLL
GND = Pin 24 Analog ground for 48MHz PLL
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
9250-27 Rev B 02/15/01
Third party brands and names are the property of their respective owners.