鈥?/div>
PCI_E (early) - PCI: 2.1ns
Pin Configuration
*FS1/REF0
X1
X2
**FS2/PCICLK_F
*SEL_CPUF#/PCICLK0
PCICLK1
GND
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK_E
VDD48
*FS3/48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDR
REF1/FS0*
SPREAD#
VDDL
CPUCLK1
CPUCLK0/F
GNDL
GND
PCI_STOP#
VDDA
CPU_STOP#
PD#
DIV/4#
GND
28 Pin 209mil SSOP
*These inputs have a 120K pull up to VDD
**These inputs have a 120K pull down to GND
Block Diagram
Functionality
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
33.33
63.33
69.99
66.66
97.00
96.22
91.50
83.33
50.00
95.25
105.00
100.00
66.66
126.35
139.65
133.33
PCI
16.66
31.66
35.00
33.33
32.33
32.07
30.50
27.77
16.66
31.75
35.00
33.33
16.66
31.66
35.00
33.33
X1
X2
CPU_STOP#
OSC
2
REF (1:0)
FS (3:0)
PLL
Spread
Spectrum
Glitch
Free
Control
Logic
/4
CPU
STOP
CPU
STOP
/2
/3
BUS
STOP
2
CPUCLK 1
CPUCLK0/F
PD#
Div4#
SPREAD#
SEL_CPUF#
5
PCICLK (4:0),
PCICLK_E
PCI_STOP#
PCICLK_F
PLL2
48MHz
9248-157 Rev A - 1/16/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
ICS9248-157