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ICS9248-77 Datasheet

  • ICS9248-77

  • Frequency Timing Generator for PENTIUM II Systems

  • 14頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-77
Frequency Timing Generator for PENTIUM II Systems
General Description
The ICS9248-77 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
the ICS9212-01.
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without resorting
to board design iterations or costly shielding. The
ICS9248-
77
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
The CPU/2 clocks are inputs to the DRCG.
Pin Configuration
Features
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Generates the following system clocks:
- 3 - CPUs @ 2.5V, up to 150MHz.
- 3 - IOAPIC @ 2.5V, PCI or PCI/2
- 3 - 3V66MHz @ 3.3V.
- 11 - PCIs @ 3.3V.
- 1 - 48MHz, @ 3.3V fixed.
- 1 - 24MHz, @ 3.3V fixed.
- 1 - CPU/2, @ 2.5V.
鹵 .25% center spread, or 0 to -.5% down spread.
Uses external 14.318MHz crystal.
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
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Block Diagram
Key Specification
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CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <500ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
9248-77 Rev C 10/20/99
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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