鈥?/div>
REF Output jitter < 1000ps
Pin Configuration
PCICLK
VDD48
FS0/48MHz
FS1/48MHz#
GND48
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT3
CPUCLKC3
VDDCPU
REF
SPREAD#
GNDREF
X1
X2
VDDREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL100/133
GNDPCI
VDDA
GNDA
PD#
VDDCPU
CPUCLKT4
CPUCLKC4
GNDCPU
CPUCLKT5
CPUCLKC5
VDDCPU
CPUCLKT6
CPUCLKC6
GNDCPU
CPUCLKT7
CPUCLKC7
VDDCPU
MULTSEL0
MULTSEL1
GND
GNDI REF
I REF
VDDI REF
48-Pin SSOP and TSSOP
Functionality
SEL133/
100
0
0
0
0
1
1
1
1
FS0
0
0
1
1
0
0
1
1
FS1
0
1
0
1
0
1
0
1
Function
PLL2
Block Diagram
48MHz
48MHz#
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
Active 100MHz
100MHz Test Mode
100MHz Test Mode
Tristate all outputs
Active 133MHz
133MHz Test Mode
Active 200MHz
Reserved
PD#
SPREAD#
MULTSEL(1:0)
SEL100/133
FS(1:0)
Control
Logic
Config.
Reg.
PCI
DIVDER
ICS9248-150
REF
CPU
DIVDER
8
8
CPUCLKT (7:0)
CPUCLKC (7:0)
PCICLK
Analog Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
I REF
Digital Power Group
VDDREF, GNDREF = REF, Xtal
9248-150 Rev B 06/12/01
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