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ICS9248-146 Datasheet

  • ICS9248-146

  • Frequency Generator & Integrated Buffers for Celeron & PII/I...

  • 194.85KB

  • 16頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-146
Frequency Generator & Integrated Buffers for Celeron & PII/III鈩?/div>
Recommended Application:
Single chip clock solution for SIS630S chipsets.
Output Features:
鈥?/div>
3- CPUs @ 2.5V
鈥?/div>
13 - SDRAM @ 3.3V
鈥?/div>
6- PCI @3.3V,
鈥?/div>
2 - AGP @ 3.3V
鈥?/div>
1- 48MHz, @3.3V fixed.
鈥?/div>
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
鈥?/div>
2- REF @3.3V, 14.318MHz.
Features:
鈥?/div>
Up to 166MHz frequency support
鈥?/div>
Support FS0-FS3 trapping status bit for I
2
C read back.
鈥?/div>
Support power management: CPU, PCI, SDRAM stops
and Power down Mode form I
2
C programming.
鈥?/div>
Spread spectrum for EMI control (0 to -0.5%, 鹵 0.25%).
鈥?/div>
Uses external 14.318MHz crystal
Skew Specifications:
鈥?/div>
CPU - CPU: < 175ps
鈥?/div>
SDRAM - SDRAM < 250ps (except SDRAM12)
鈥?/div>
PCI - PCI: < 500ps
鈥?/div>
CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDA
*
(AGPSEL)REF0
1
*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1
These are double strength.
Block Diagram
Functionality
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
66.67
100.00
166.67
133.33
66.67
100.00
100.00
133.33
112.00
124.00
138.00
150.00
66.67
100.00
150.00
160.00
SDRAM PCICLK
66.67
100.00
166.67
133.33
100.00
66.67
133.33
100.00
112.00
124.00
138.00
150.00
133.33
150.00
100.00
120.00
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.60
31.00
34.50
30.00
33.33
30.00
30.00
30.00
AGP SEL AGP SEL
=0
=1
66.67
50.00
66.67
50.00
66.66
55.56
66.67
50.00
66.67
50.00
66.67
50.00
66.67
50.00
66.67
50.00
67.20
56.00
62.00
46.50
69.00
51.75
60.00
50.00
66.67
60.00
60.00
60.00
50.00
50.00
50.00
48.00
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
2
REF(1:0)
CPU
DIVDER
Stop
3
CPUCLK (2:0)
SDRAM
DIVDER
Stop
13
SDRAM (12:0)
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
PCI
DIVDER
Stop
5
PCICLK (4:0)
PCICLK_F
AGP
DIVDER
Config.
Reg.
2
AGP (1:0)
9248-146 RevA- 4/23/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-146

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