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ICS9248-136 Datasheet

  • ICS9248-136

  • Frequency Generator & Integrated Buffers for K7 Processor

  • 16頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-136
Advance Information
Frequency Generator & Integrated Buffers for K7 Processor
Recommended Application:
Single chip clock solution for SIS 730S K7 chipset.
Output Features:
鈥?/div>
1 - Differential pair open drain CPU clock
鈥?/div>
1 - Single-ended open drain CPU clock
鈥?/div>
13 - SDRAM @ 3.3V
鈥?/div>
6- PCI @3.3V,
鈥?/div>
2 - AGP @ 3.3V
鈥?/div>
1- 48MHz, @3.3V fixed.
鈥?/div>
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
鈥?/div>
2- REF @3.3V, 14.318MHz.
Features:
鈥?/div>
Up to 166MHz frequency support
鈥?/div>
Support FS0-FS3 trapping status bit for I
2
C read back.
鈥?/div>
Support power management: CPU, PCI, SDRAM stop
and Power down Mode from I
2
C programming.
鈥?/div>
Spread spectrum for EMI control (0 to -0.5%, 鹵 0.25%).
鈥?/div>
Uses external 14.318MHz crystal
Skew Specifications:
鈥?/div>
CPU - CPU: < 175ps
鈥?/div>
SDRAM - SDRAM < 250ps
鈥?/div>
PCI - PCI: < 500ps
鈥?/div>
CPU - SDRAM: < 500ps
鈥?/div>
CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDA
*
(AGPSEL)REF1
1
*(FS3)REF0
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDCPU
CPUCLKT0
CPUCLKC0
CPUCLKT1
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Block Diagram
Functionality
FS3 FS2 FS1 FS0
CPU
100.00
100.00
100.00
100.00
112.00
125.00
124.00
133.33
133.33
150.00
111.11
110.00
166.67
90.00
48.00
45.00
SDRAM PCICLK
100.00
133.33
150.00
66.67
112.00
100.00
124.00
100.00
133.33
150.00
166.67
165.00
166.67
90.00
48.00
60.00
33.33
33.33
30.00
33.33
33.60
31.25
31.00
33.33
33.33
30.00
33.33
33.00
33.33
30.00
32.00
30.00
AGP
SEL = 0
66.67
66.67
60.00
66.67
67.20
62.50
62.00
66.67
66.67
60.00
66.67
66.00
66.67
60.00
64.00
60.00
AGP
SEL = 1
50.00
50.00
50.00
50.00
56.00
50.00
46.50
50.00
50.00
50.00
55.56
55.00
55.56
45.00
48.00
45.00
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
2
REF (1:0)
CPU
DIVDER
Stop
CPUCLKC0
2
CPUCLKT (1:0)
SDRAM (12:0)
SDRAM
DIVDER
Stop
13
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
PCI
DIVDER
Stop
5
PCICLK (4:0)
PCICLK_F
AGP
DIVDER
Config.
Reg.
2
AGP (1:0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
9248-136 Rev - 03/29/01
Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
ICS9248-136

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