鈥?/div>
CPU - PCI: 1 - 4ns
Pin Configuration
VDDREF
1
* REF0/FS3
GND
X1
X2
VDDPCI
*PCICLK0/FS1
*PCICLK1/FS2
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDSDR
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1
VDDLCPU
CPUCLK0
CPUCLK1
GND
CPUCLK2
VDDSDR
SDRAM13
SDRAM12
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GNDSDR
SDRAM7
SDRAM6
VDDSDR
SDRAM5
SDRAM4
VDDSDR
1
48MHz/FS0*
24_48MHz/CPU2.5_3.3#*
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
48MHz
24_48MHz
Functionality
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.8
97.0
70.0
95.0
95.0
112.0
97.0
96.2
SDRAM
(MHz)
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
97.0
105.0
95.0
126.7
112.0
129.3
96.2
PCICLK
(MHz)
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.2
32.1
2
REF (1:0)
PLL1
Spread
Spectrum
FS(3:0)
4
CPU
CLOCK
DIVDER
SDRAM
CLOCK
DIVDER
3
CPUCLK (2:0)
LATCH
14
SDRAM (13:0)
Control
CPU2.5_3.3#
SDATA
SCLK
Logic
Config.
Reg.
PCI
CLOCK
DIVDER
7
PCICLK (6:0)
9248-126 Rev C 9/6/00
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-126