鈥?/div>
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
PLL2
Block Diagram
48MHz
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
24_48MHz
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <580ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ = 1.3ns)
CPU to PCI Output Offset: 0.0 - 1.5ns (typ = 1.0ns)
CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ = 2.0ns)
SEL24_48#
I C
2
REF(1:0)
CPU
DIVDER
CPUCLK (3:0)
IOAPIC
DIVDER
IOAPIC (2:0)
Control
Logic
Config.
Reg.
{
PCI
DIVDER
PCICLK (10:0)
PCICLK_F
SDATA
SCLK
FS(4:0)
PD#
3V66
DIVDER
3V66 (2:0)
9248-107 RevA - 5/21/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.