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ICS9178-03 Datasheet

  • ICS9178-03

  • 245 MHz Clock Generator and Integrated Buffer for PowerPC...

  • 8頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9178-03
245 MHz Clock Generator and Integrated Buffer for PowerPC聶
General Description
The
ICS9178-03
generates all clocks required for high speed
PowerPC RISC microprocessor systems. Generating clocks
in phase with an external reference frequency allows the
ICS9178-03
to be used as a multiplying zero delay buffer.
Three different multiplying factors are externally selectable.
These factors can be customized for specific applications. An
external frequency can be directly applied to aid system
testing. With 2X processor clock speeds up to 245 MHz,
PECL outputs are provided. User selectable frequency ratios
are available for PCLK/BCLK and PCLK/XCLK. Each pair of
clocks outputs have separate supply pins to minimize output
jitter and allow them to operate at 5V, 3.3V or custom voltage
levels.
Features
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Generates 2 PECL 2x processor, 2 TTL/CMOS 1x
processor and 10 selectable bus clocks
2XPCLK ranges from 75 MHz to 245 MHz (5V or
5V/3.3V mixed supply) or 60 to 170 MHz (3.3V only)
Asymmetric duty cycle bus clock for PowerPC
Bus to processor clock skews less than 鹵250ps
2XPCLK to PCLK skew controlled at 300 鹵300ps
Selectable reference multiplying factors
Selectable PCLK/BCLK and PCLK/XCLK ratios
Separate supplies allow 5V and 3.3V output mix
3.0V - 5.5V supply range
44-pin PQFP package
Applications
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Ideal for high-speed systems based on PowerPC
Block Diagram
PowerPC is a trademark of Motorola Corporation.
ICS9178-03 Rev C 02/12/98P
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.

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