鈮?/div>
80 MHz
Cyc to Cyc jitter: <150ps
Output duty cycle 45-55%
Guarantees +85擄C operational condition.
8-pin SOIC/TSSOP
Reference input
Functionality
FSIN_1 FSIN_0
MHz
0
0
14.318 MHz in --> 27MHz out
0
1
14.318MHz -->14.318MHz out
1
0
27.00MHz in --> 27.00MHz out
1
1
48.00MHz in -->48.00 MHz out
Spread % default
-0.8 down spread
-1.00 down spread
-1.25 down spread
-0.8 down spread
Block Diagram
REFOUT
CLKIN
PLL1
Spread
Spectrum
Spectrum
CLKOUT
CLKOUT
PD#
SDATA
SD
SCLK
FS_IN0:1
Control
Logic
Config.
Reg.
0698D鈥?0/05/04