鈥?/div>
27MHz, 48MHz and 66MHz reference clock input
Pin Configuration
GND
X1 _CLKIN
X2
GNDA
VDDA
VDD
GND
* * CLKOUT/FS_IN0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDREF
VDDREF_SEL_2.5V/3.3V# ^
REF_OUT/VDDREF_SEL_1.8V * *
**REF_Stop
^PD#
SCLK
SDATA
^SPREAD_ENABLE/FS_IN1
16-pin TSSOP
Notes:
** Internal pull-down
^ Internal pull-up
Input Select Functionality
FS_IN1 FS_IN0 MHZ
0
0
1
1
0
1
0
1
14.318 in 27.00 out
14.318 in/out
27.00 in/out
48.00 in/out
66.66 in/out
Default Spread %
-0.8% downspread
-0.8% downspread
-0.8% downspread
-0.8% downspread
Block Diagram
REFOUT
CLKIN
PLL1
Spread
Spectrum
Spectrum
CLKOUT
CLKOUT
REF Voltage Select Functionality
Pin14
0
0
1
1
Pin15
0
1
0
1
REF Voltage
N/A
1.8V
2.5V
3.3V
SPREAD#
PD#
REF_STOP
SDAT
SD A
SCLK
FS_IN0:1
Control
Logic
Config.
Reg.
0506D鈥?8/16/04