鈥?/div>
Twelve selectable CPU clocks operate up to 83.3MHz
Maximum CPU jitter of 鹵 200ps
Six BUS clocks support sync or async bus operation
250ps skew window for CPU outputs, 500ps skew
window for BUS outputs
CPU clocks BUS clocks skew 0-2ns (CPU early)
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range, CPU(1:6) outputs 2.5V(2.375-
2.62V) VDD option
32-pin SOJ package
Logic inputs latched at Power-On for frequency selection
saving pins as Input/Output
48 MHz clock for USB support and 24 MHz clock for FD
Block Diagram
Pin Configuration
32-Pin SOJ
3.3V鹵10%, 0-70
擄
C
Crystal (X1, X2) = 14.31818 MHz
Functionality
BUS (1:6)MHz
BSEL=1
25
30
33.3
REF/4
27.5
37.5
41.7
Tristate
VDD Groups:
VDD1 = X1, X2, REF/BSEL
VDD2 = CPU(1:6)
VDD3 = CPU(7:12) & PLL Core
VDD4 = BUS(1:6)
VDD5 = 48/24 MHz
Latched Inputs:
L1 = BSEL
L2 = FS0
L3 = FS1
L4 = FS2
ADDRESS
SELECT
FS2 FS1 FS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CPU(1:12)
(MHz)
50
60
66.6
REF/2
55
75
83.3
Tristate
48MHz
BSEL=0
32
48
32
48
32
48
REF/3
REF/2
32
48
32
48
32
48
Tristate Tristate
24MHz
24
24
24
REF/4
24
24
24
Tristate
REF
REF
REF
REF
REF
REF
REF
REF
Tristate
Pentium is a trademark on Intel Corporation.
9169C-273RevC031897
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.