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ICS9148F-26 Datasheet

  • ICS9148F-26

  • Frequency Generator & Integrated Buffers for PENTIUM/ProTM

  • 17頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9148-26
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
General Description
The
ICS9148-26
generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Features include two CPU, six PCI and fourteen SDRAM clocks.
Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at 鹵0.5% or 鹵1.5% modulation to reduce the
EMI. Serial programming I
2
C interface allows changing
functions, stop clock programing and Frequency selection.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up. It is not recommended to use I/O
dual function pin for the slots (ISA, PIC, CPU, DIMM). The
add on card might have a pull up or pull down.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50鹵5% duty cycle. The REF and 24 and 48
MHz clock outputs typically provide better than 0.5V/ns slew
rates into 20pF.
Features
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3.3V outputs: SDRAM, PCI, REF, 48/24MHz
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.2 ns.
No external load cap for C
L
=18pF crystals
鹵250 ps CPU, PCI clock skew
250ps (cycle to cycle) CPU jitter @ 66.66MHz
Smooth frequency switch, with selections from 50 to
133 MHz CPU.
I
2
C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs (with series R)
<6ns propagation delay SDRAM form Buffer Input
Pin Configuration
Block Diagram
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:4)
VDD3 = SDRAM (0:13), supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:1)
9148-26 Rev D 07/23/98
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.

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