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ICS9148-37 Datasheet

  • ICS9148-37

  • Frequency Generator & Integrated Buffers for PENTIUM/Pro

  • 16頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9148-37
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
General Description
The
ICS9148-37
is the single chip clock solution for
Desktop/Notebook designs using the VIA MVP3 style
chipset. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The
ICS9148-
37
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection. The
SD_SEL latched input allows the SDRAM frequency to
follow the CPUCLK frequency(SD_SEL=1) or the AGP
clock frequency(SD_SEL=0)
Features
鈥?/div>
Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU or AGP
- 2 REF (3.3V) @ 14.318MHz
Skew characteristics:
- CPU 鈥?CPU<250ps
- SDRAM 鈥?SDRAM < 250ps
- CPU 鈥?SDRAM < 250ps
- CPU鈥揂GP: < 1ns
- CPU(early) 鈥?PCI : 1-4ns
Supports Spread Spectrum modulation +0.25, 鹵0.6%
Serial I
2
C interface for Power Management,
Frequency Select, Spread Spectrum.
Efficient Power management scheme through PCI and
CPU STOP CLOCKS.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
0143G鈥?8/04/04
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs

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