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Generates 46.6 MHz and 33.868 MHz clocks
Buffered REFCLK output
0.20% frequency accuracy
100ps one sigma jitter maintains 16-bit performance
Output rise/fall times less than 2.5ns
On-chip loop filter components
3.0V - 5.5V supply range
8-pin, 150-mil SOIC package Advance Information
Block Diagram
Pin Configuration
8-Pin SOIC
Functionality
X1 (MHz)
-
14.318
PD#
0
1
33.9
(MHz)
Low
33.868
46.6
(MHz)
Low
46.6
14.3
(MHz)
Low
14.318
Note: PD# (Pin 8) and OE (Pin 4) are internally pulled-up
to VDD and therefore may be left disconnected or driven by
open collector logic.
9120-11 Rev B 012197