Express鈩?systems. In some PCI Express鈩?/div>
systems, such as those found in desktop PCs,
the PCI Express鈩?clocks are generated from a
low bandwidth, high phase noise PLL frequency synthesizer.
In these systems, a jitter attenuator may be required to
attenuate high frequency random and deterministic jitter
components from the PLL synthesizer and from the system
board. The ICS874002 has 3 PLL bandwidth modes:
200KHz, 400KHz, and 800KHz. The 200KHz mode will pro-
vide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. 400KHz provides an
intermediate bandwidth that can easily track triangular
spread profiles, while providing good jitter attenuation.
800KHz bandwidth provides the best tracking skew and will
pass most spread profiles, but the jitter attenuation will not be
as good as the lower bandwidth modes. Because some 2.5
Gb serdes have x20 multipliers while others have than x25
multipliers, the 874002 can be set for 1:1 mode or 5/4
multiplication mode (i.e. 100MHz input/125MHz output) using
the F_SEL pin.
F
EATURES
鈥?/div>
(2) Differential LVDS output pairs
鈥?/div>
(1) Differential clock input
鈥?/div>
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
鈥?/div>
Output frequency range: 98MHz - 160MHz
鈥?/div>
Input frequency range: 98MHz - 128MHz
鈥?/div>
VCO range: 490MHz - 640MHz
鈥?/div>
Cycle-to-cycle jitter: 50ps (maximum) design target
鈥?/div>
3.3V operating supply
鈥?/div>
3 bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
鈥?/div>
0擄C to 70擄C ambient operating temperature
ICS
PLL B
ANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~200KHz
Float = PLL Bandwidth: ~400KHz (Default)
1 = PLL Bandwidth: ~800KHz
The ICS874002 uses ICS 3
rd
Generation FemtoClock
TM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express鈩?add-in cards.
B
LOCK
D
IAGRAM
OE PU
F_SEL PD
BW_SEL Float
0 = ~200KHz
Float = ~400KHz
1 = ~800KHz
CLK PD
nCLK PU
FB_IN PD
nFB_IN PU
梅5
(fixed)
P
IN
A
SSIGNMENT
nQA0
V
DDO
FB_OUT
nFB_OUT
MR
BW_SEL
nc
V
DDA
F_SEL
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QA0
V
DDO
QA1
nQA1
nFB_IN
FB_IN
GND
nCLK
CLK
OE
0
1
梅5
(default)
QA0
nQA0
QA1
nQA1
梅4
Phase
Detector
VCO
490 - 640 MHz
ICS874002
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
FB_OUT
nFB_OUT
G Package
Top View
MR PD
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
874002AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2005
1
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英文版
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER
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英文版
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350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
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LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CH...
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