HiPerClockS鈩?/div>
member of the HiPerClockS鈩amily of High Per-
formance Clock Solutions from ICS. The CLK,
nCLK pair can accept most standard differential
input levels. The ICS8735-21 has a fully integrated PLL and
can be configured as zero delay buffer, multiplier or divider,
and has an output frequency range of 31.25MHz to 700MHz.
The reference divider, feedback divider and output divider
are each programmable, thereby allowing for the following out-
put-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.
The external feedback allows the device to achieve 鈥渮ero
delay鈥?between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system test
and debug purposes. In bypass mode, the reference clock
is routed around the PLL and into the internal output dividers.
ICS
B
LOCK
D
IAGRAM
PLL_SEL
梅1, 梅2, 梅4, 梅8,
梅16, 梅32, 梅64
P
IN
A
SSIGNMENT
0
1
Q
nQ
QFB
nQFB
CLK
nCLK
MR
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
SEL1
SEL0
V
CC
PLL_SEL
V
CCA
SEL3
V
CCO
Q
nQ
CLK
nCLK
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
nFB_IN
ICS8735-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
SEL0
SEL1
SEL2
SEL3
MR
8735AM-21
www.icst.com/products/hiperclocks.html
1
REV. D OCTOBER 27, 2003