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ICS8602BYT Datasheet

  • ICS8602BYT

  • ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

  • 10頁

  • ICS

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PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8602
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
F
EATURES
鈥?/div>
Fully integrated PLL
鈥?/div>
9 LVCMOS/LVTTL outputs, 7鈩?typical output impedance
鈥?/div>
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
鈥?/div>
Output frequency range: 15.625MHz to 250MHz
鈥?/div>
Input frequency range: 15.625MHz to 250MHz
鈥?VCO range: 250MHz to 500MHz
鈥?External feedback for 鈥渮ero delay鈥?clock regeneration
with configurable frequencies
鈥?Cycle-to-cycle jitter: 36ps (typical)
鈥?Output skew: 125ps (maximum)
鈥?Static Phase Offset: TBD鹵100ps (typical)
鈥?3.3V supply voltage
鈥?0擄C to 70擄C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8602 is a high performance, low skew,
1-to-9 Differential-to-LVCMOS/LVTTL Zero De-
HiPerClockS鈩?/div>
lay Buffer and a member of the HiPerClockS鈩?/div>
family of High Performance Clocks Solutions
from ICS. The CLK, nCLK pair can accept most
standard differential input levels. The VCO operates at a fre-
quency range of 250MHz to 500MHz. The external feedback
allows the device to achieve 鈥渮ero delay鈥?between the input
clock and the output clocks. The device is designed only for
1:1 input/output frequency ratios. The output divider allows a
wide input/output frequency range with the 250MHz to
500MHz VCO. The PLL_SEL pin can be used to bypass the
PLL for system test and debug purposes. In bypass mode,
the reference clock is routed around the PLL and into the in-
ternal output dividers.The low impedance LVCMOS/LVTTL out-
puts are designed to drive 50鈩?series or parallel terminated
transmission lines. The effective fanout can be doubled by
utilizing the ability of the outputs to drive two series termi-
nated lines. The differential reference clock input will accept
any differential signal levels.
,&6
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
PLL_SEL
V
DDO
V
DDO
GND
GND
Q6
Q8
Q7
Q0
SEL0
SEL1
Q1
32 31 30 29 28 27 26 25
V
DDA
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
FB_IN
V
DDO
Q0
GND
Q1
V
DDO
Q2
GND
24
23
22
Q2
梅2
梅4
梅8
梅16
V
DDO
Q5
GND
Q4
V
DDO
Q3
GND
MR/nOE
V
DD
CLK
nCLK
GND
Q3
Q4
Q5
Q6
0
CLK
nCLK
PLL
1
ICS8602
21
20
19
18
17
DIV_SEL0
DIV_SEL1
GND
FB_IN
PLL_SEL
MR/nOE
Q7
Q8
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8602BY
www.icst.com/products/hiperclocks.html
1
REV. F APRIL 16, 2003

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