HiPerClockS鈩?/div>
member of the HiPerClockS鈩?family of High Per-
formance Clock Solutions from ICS. The PCLK,
nPCLK pairs can accept most standard differen-
tial input levels. Internal termination is provided on each dif-
ferential input pair. The ICS854057 operates using a 2.5V sup-
ply voltage. The fully differential architecture and low propa-
gation delay make it ideal for use in high speed multiplexing
applications. The select pins have internal pulldown resistors.
Leaving one input unconnected (pulled to logic low by the in-
ternal resistor) will transform the device into a 2:1 multiplexer.
The SEL1 pin is the most significant bit and the binary num-
ber applied to the select pins will select the same numbered
data input (i.e., 00 selects PCLK0, nPCLK0).
ICS
B
LOCK
D
IAGRAM
VT0
50
PCLK0
nPCLK0
VT1
50
PCLK1
nPCLK1
00
VT2
50
PCLK2
nPCLK2
VT3
50
PCLK3
nPCLK3
SEL1
Pulldown
SEL0
Pulldown
50
50
01
10
11
Q
nQ
50
50
P
IN
A
SSIGNMENT
V
DD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
PCLK3
VT3
nPCLK3
Q
nQ
PCLK2
VT2
nPCLK2
GND
ICS854057
20-Lead TSSOP
4.40mm x 6.50mm x 0.925mm body package
G Package
Top View
854057AG
www.icst.com/products/hiperclocks.html
1
REV. A JULY 18, 2005