HiPerClockS鈩?/div>
family of High Performance Clock Solutions from
ICS. The low impedance LVCMOS out-
puts are designed to drive 50鈩?series or parallel
terminated transmission lines. The effective fanout can be in-
creased from 18 to 36 by utilizing the ability of the outputs to
drive two series terminated lines. The differential clock
input is designed to accept any differential input levels
including LVPECL.
,&6
The ICS83940-01 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
VDDO
GND
Q0
Q1
Q2
Q3
Q4
Q5
CLK_SEL
CLK0
nCLK0
LVCMOS_CLK
GND
Q0
1
32 31 30 29 28 27 26 25
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q17
Q16
Q15
GND
Q14
Q13
Q12
VDDO
24
23
22
Q6
Q7
Q8
VDDO
Q9
Q10
Q11
GND
GND
LVCMOS_CLK
Q1 - Q16
CLK_SEL
CLK
nCLK
ICS83940-01
21
20
19
18
17
Q17
VDDI
VDDO
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940AY-01
www.icst.com/products/hiperclocks.html
1
REV. A JULY 31, 2001