ICS. The ICS8344 is designed to translate any
differential signal levels to LVCMOS levels. The
low impedance LVCMOS outputs are designed to drive 50鈩?/div>
series or parallel terminated transmission lines. The effective
fanout can be increased to 48 by utilizing the ability of the
outputs to drive two series terminated lines. Redundant clock
applications can make use of the dual clock input. The dual
clock inputs also facilitate board level testing. ICS8344 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and
2.5V output operating supply modes.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8344 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q8
Q9
VDDO
GND
Q10
Q11
Q12
Q13
VDDO
GND
Q14
Q15
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
0
1
Q0 - Q7
OE1
O8 - Q15
OE2
O16 - Q23
OE3
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8344
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8344
www.icst.com
REV. B FEBRUARY 2, 2001
1
OE1
OE2
OE3
CLK0
nCLK0
VDDI
GND
CLK1
nCLK1
VDDI
GND
CLK_SEL
48-Lead LQFP
Y Package
Top View