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ICS8305AG Datasheet

  • ICS8305AG

  • LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS...

  • 16頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS8305
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
F
EATURES
鈥?4 LVCMOS/LVTTL outputs
鈥?Selectable differential or LVCMOS/LVTTL clock inputs
鈥?/div>
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
鈥?LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
鈥?Maximum output frequency: 350MHz
鈥?Output skew: 35ps (maximum)
鈥?Part-to-part skew: 700ps (maximum)
鈥?Additive phase jitter, RMS: 0.04ps (typical)
鈥?3.3V core, 3.3V, 2.5V or 1.8V output operating supply
鈥?0擄C to 70擄C ambient operating temperature
鈥?Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8305 is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
HiPerClockS鈩?/div>
member of the HiPerClockS鈩?family of High
Performance Clock Solutions from ICS. The
ICS8305 has selectable clock inputs that accept
either differential or single ended input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A sepa-
rate output enable pin controls whether the outputs are in the
active or high impedance state.
ICS
Guaranteed output and part-to-part skew characteristics make
the ICS8305 ideal for those applications demanding well de-
fined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
LVCMOS_CLK
CLK
nCLK
CLK_SEL
Q2
P
IN
A
SSIGNMENT
GND
OE
V
DD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
V
DDO
Q1
GND
Q2
V
DDO
Q3
GND
0
0
1
1
Q0
Q1
ICS8305
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
Q3
OE
8305AG
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 26, 2004
1

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