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ICS7973DI147 Datasheet

  • ICS7973DI147

  • LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY...

  • 16頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
EATURES
鈥?/div>
Fully integrated PLL
鈥?/div>
14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync
鈥?/div>
Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
鈥?/div>
CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
鈥?/div>
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
鈥?/div>
Output frequency range: 10MHz to 150MHz
鈥?/div>
VCO range: 240MHz to 500MHz
鈥?/div>
Output skew: 200ps (maximum)
鈥?/div>
Cycle-to-cycle jitter, (all banks 梅 4): 55ps (maximum)
鈥?/div>
Full 3.3V supply voltage
鈥?/div>
-40擄C to 85擄C ambient operating temperature
鈥?/div>
Pin compatible with MPC973
鈥?/div>
Compatible with PowerPC鈩?and Pentium鈩?Microprocessors
G
ENERAL
D
ESCRIPTION
ICS
HiPerClockS鈩?/div>
The ICS87973I-147 is a LVCMOS/LVTTL clock
generator and a member of the HiPerClockS鈩am-
ily of High Performance Clock Solutions from ICS.
The ICS87973I-147 has three selectable inputs
and provides 14 LVCMOS/LVTTL outputs.
The ICS87973I-147 is a highly flexible device. The three select-
able inputs (1 differential and 2 single ended inputs) are often
used in systems requiring redundant clock sources. Up to three
different output frequencies can be generated among the three
output banks.
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output fre-
quency range is 10MHz to 150MHz. The input frequency range is
6MHz to 120MHz.
The ICS87973I-147 also has a QSYNC output which can be
used for system synchronization purposes. It monitors Bank A
and Bank C outputs and goes low one period prior to coincident
rising edges of Bank A and Bank C clocks. QSYNC then goes
high again when the coincident rising edges of Bank A and
Bank C occur. This feature is used primarily in applications where
Bank A and Bank C are running at different frequencies, and is
particularly useful when they are running at non-integer mul-
tiples of one another.
Example Applications:
1.
System Clock generator:
Use a 16.66MHz reference
clock to generate eight 33.33MHz copies for PCI and
four 100MHz copies for the CPU or PCI-X.
2.
Line Card Multiplier:
Multiply differential 62.5MHz from
a back plane to single-ended 125MHz for the line Card
ASICs and Gigabit Ethernet Serdes.
3.
Zero Delay buffer for Synchronous memory:
Fan out
up to twelve 100MHz copies from a memory controller
reference clock to the memory chips on a memory module
with zero delay.
P
IN
A
SSIGNMENT
EXT_FB
GNDO
GNDO
GNDO
V
DDO
V
DDO
QB0
QB1
QB2
QB3
QFB
V
DD
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
V
DDO
QA2
GNDO
QA1
V
DDO
QA0
GNDO
VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
42
43
44
45
46
47
48
49
50
51
52
1
GNDI
FSEL_FB0
FSEL_FB1
QSYNC
GNDO
QC0
V
DDO
QC1
FSEL_C0
FSEL_C1
QC2
V
DDO
QC3
GNDO
INV_CLK
25
24
23
22
21
ICS87973I-147
20
19
18
17
16
15
14
2
nMR/OE
3
FRZ_CLK
4
FRZ_DATA
5 6
FSEL_FB2
PLL_SEL
7 8
REF_SEL
CLK_SEL
9 10 11 12 13
CLK0
CLK1
CLK
nCLK
V
DDA
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
87973DYI-147
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 26, 2003

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