PRELIMINARY INFORMATION
ICS650-07C
Networking Clock Source
Description
The ICS650-07C is a low cost, low jitter, high
performance clock synthesizer for networking
applications. Using analog Phase-Locked Loop
(PLL) techniques, the device accepts a 12.5 MHz
or 25.00 MHz clock or fundamental mode crystal
input to produce multiple output clocks for
networking chips, PCI devices, SDRAM, and
ASICs. The ICS650-07C outputs all have 0 ppm
synthesis error.
See the MK74CB214, ICS551, and ICS552-01 for
non-PLL buffer devices which produce multiple
low-skew copies of these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay
buffers that can synchronize outputs and other
needed clocks.
Features
鈥?Packaged in 20 pin narrow (150 mil) SSOP (QSOP)
鈥?12.5 MHz or 25.00 MHz fundamental crystal or
clock input
鈥?Six output clocks with selectable frequencies
鈥?SDRAM frequencies of 67, 83, 100, and 133 MHz
鈥?Buffered crystal reference output
鈥?Zero ppm synthesis error in all clocks
鈥?Ideal for PMC-Sierra鈥檚 ATM switch chips
鈥?Full CMOS output swing with 25 mA output drive
capability at TTL levels
鈥?Advanced, low power, sub-micron CMOS process
鈥?3.0V to 5.5V operating voltage
Block Diagram
VDD
GND
2
2
2
Output
Buffer
CLKA1
CLKA2
CLKB1
CLKB2
CLKC1
CLKC2
REFOUT
ACS1,0
BCS1,0
CCS
12.5 MHz or
25.00 MHz
crystal or clock
X1
梅2
2
Clock Synthesis
and Control
Circuitry
梅2
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
X2
Clock
Buffer/
Crystal
Oscillator
OE (all outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
1
Revision 101399
Printed 11/28/00
Integrated Circuit Systems, Inc. 鈥?525 Race Street 鈥?San Jose 鈥?CA 鈥?95126鈥?408)295-9800tel 鈥?www.icst.com
MDS 650-07C A
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