PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Description
The ICS650-14B is a low cost, low jitter, high
performance clock synthesizer customized for
networking systems applications. Using analog
Phase-Locked Loop (PLL) techniques, the device
accepts a 25.0 MHz clock or fundamental mode
crystal input to produce multiple output clocks of
one fixed 25.0 MHz, a four (plus one) frequency
selectable bank, and two frequency selectable
clocks. All output clocks are frequency locked
together. The ICS650R-14B outputs
all have 0 ppm synthesis error.
Features
鈥?Packaged in 20 pin (150 mil) SSOP (QSOP)
鈥?25.00 MHz fundamental crystal or clock input
鈥?One fixed output clock of one 25.0 MHz
鈥?One bank of four frequency selectable
output clocks
鈥?Three frequency selectable clock outputs
鈥?Zero ppm synthesis error in all clocks
鈥?Ideal for networking systems
鈥?Full CMOS output swing
鈥?Advanced, low power, sub-micron CMOS process
鈥?3.0V to 5.5V operating voltage
鈥?Industrial temperature range available
Block Diagram
VDD
GND
2
SELA 0:1
SELB 0:1
SELC
2
2
2
Output
Buffer
4
CLKA 1:4
CLKA5
CLKB
CLKC
Clock Synthesis
and Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
25.00 MHz
crystal or clock
X1/ICLK
Clock
Buffer/
Crystal
Oscillator
Output
Buffer
25.00 MHz
X2
OE (All outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
1
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. 鈥?525 Race Street 鈥?San Jose 鈥?CA 鈥?95126鈥?408)295-9800tel鈥?www.icst.com
MDS 650-14B A
1
2
3
4
