PRELIMINARY INFORMATION
I C R O
C
LOC K
Description
The ICS620-01 is a low cost, low jitter, high
performance clock synthesizer for digital still
cameras. Using analog Phase-Locked Loop
(PLL) techniques, the device uses a
14.318 MHz crystal input to produce multiple
output clocks required in the camera. It
provides selectable NTSC/PAL clock, a
selectable processor clock, a selectable CCD
clock, and a selectable interface clocks. Most
clocks are generated to a very low ppm
synthesis error rate.
All clocks can be turned off using a power
down mode. Custom versions with user-
defined frequencies and power down modes
are available in 6-8 weeks.
ICS620-01
Digital Still Camera Clock Source
Features
鈥?Packaged in 28 pin, 150 mil wide SSOP (QSOP)
鈥?Provides all clocks necessary for many digital still
camera systems
鈥?All clocks are frequency locked together
鈥?Interface clock for USB, P1394, or UART
鈥?Saves space over multiple crystals and oscillators
鈥?Clocks power down when all select pins are low
鈥?Full CMOS outputs also compatible with TTL levels
鈥?+3.3 V or +5 V operation
鈥?Low power, sub-micron CMOS process
鈥?Custom versions available
Block Diagram
Output
Buffer
梅2
Output
Buffer
Output
Buffer
梅2
Output
Buffer
Output
Buffer
梅2
Output
Buffer
Output
Buffer
Output
Buffer
2
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
NTSC/PAL Clock 1
NTSC/PAL Clock 2
Processor Clock 1
Processor Clock 2
CCD Clock 1
CCD Clock 2
Interface Clock 1
Interface Clock 2
PSEL1:0
2
CSEL1:0
ISEL1:0
X1
X2
2
2
Crystal
Oscillator
14.31818
MHz
crystal
MDS 620-01 B
1
Revision 072098
Printed 12/4/00
Integrated Circuit Systems 鈥?1271 Parkmoor Ave.鈥an Jose鈥A鈥?5126鈥?408)295-9800tel鈥?408)295-9818fax
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