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Low skew outputs (50 ps maximum)
Packaged in 16 pin TSSOP
Low power CMOS technology
Operating Voltages of 2.5 V to 5 V
Output Enable pin tri-states outputs
Low skew between 1X and 1/2X outputs (100 ps
maximum)
One bank of 4 outputs at 1X
One bank of 4 outputs at 1/2X
5V tolerant input clocks
Input clock multiplexer
Block Diagram
Q0
IN A
1
Q1
Q2
Q3
P0
P1
P2
P3
IN B
0
D ivid e
by 2
S E LA
OE
MDS 552-03 B
In tegr ated C ir cu it S yst ems
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1
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