PRELIMINARY INFORMATION
I C R O
C
LOC K
Description
The ICS543 is a cost effective way to produce a
high quality clock output divided from a clock
input. The chip accepts a clock input up to
90 MHz at 5.0 V, and by using proprietary Phase
Locked Loop (PLL) techniques, produces a divide
by 3, 5, 6, or 10, or a multiply by 2 of the input
clock. There are two outputs on the chip, one
being a low-skew divide by two of the other. So,
for instance, if an 81 MHz input clock is used, the
ICS543 can produce low skew 27 MHz and
13.5 MHz clocks. The chip has an all-chip power
down mode that stops the outputs low, and an OE
pin that tri-states the outputs.
The ICS543 is a member of the ICS
ClockBlocks鈩?family of clock building blocks.
See the ICS541 and ICS542 for other clock
dividers, and the ICS300, 501, 502, and 503 for
clock multipliers.
ICS543
Clock Divider and 2X Multiplier
Features
鈥?Packaged in 8 pin SOIC
鈥?Low cost clock divider and 2X multiplier
鈥?Low skew (500ps) outputs. One is 梅 2 of other.
鈥?Easy to use with other generators and buffers
鈥?Input clock frequency up to 90 MHz at 5 V
鈥?Output clock duty cycle of 45/55
鈥?Power Down turns off chip
鈥?Output Enable
鈥?Full CMOS clock swings with 25 mA drive
capability at TTL levels
鈥?Advanced, low power CMOS process
鈥?Operating voltages of 3.0 to 5.5 V
Block Diagram
VDD GND
2
S1, S0
Divider and
Selection
Circuitry
Input Clock
梅2
Output
Buffer
CLK
Output
Buffer
CLK/2
OE (both outputs)
1
Revision 010599
Printed 12/4/00
Integrated Circuit Systems, Inc.鈥?25 Race Street鈥an Jose鈥A鈥?5126鈥?408)295-9800tel鈥?408)295-9818fax
MDS 543 A
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