PRELIMINARY INFORMATION
ICS541
PLL Clock Divider
Description
The ICS541 is a cost effective way to produce a
high quality clock output divided from a clock
input. The chip accepts a clock input up to
135 MHz at 3.3 V, and by using proprietary Phase
Locked Loop (PLL) techniques, produces a divide
by 1, 2, 4, or 8 of the input clock. There are two
outputs on the chip, one being a low-skew divide
by two of the other. So, for instance, if an 80 MHz
input clock is used, the ICS541 can produce low
skew 80 MHz and 40 MHz clocks, or 40 MHz
and 20 MHz clocks, or 20 MHz and 10MHz
clocks. The chip has an all-chip power down mode
that stops the outputs low, and an OE pin that tri-
states the outputs.
The ICS541 is a member of the ICS
ClockBlocks鈩?family of clock building blocks.
See the ICS542 and ICS543 for other clock
dividers, and the ICS300, 501, 502, and 503 for
clock multipliers.
Features
鈥?Packaged in 8 pin SOIC
鈥?Low cost clock divider
鈥?Low skew (500ps) outputs. One is 梅 2 of other.
鈥?Easy to use with other generators and buffers
鈥?Input clock frequency up to 135 MHz at 3.3 V
鈥?Input clock frequency up to 156 MHz at 5.0 V
鈥?Tolerant of poor input clock duty cycle, jitter.
鈥?Output clock duty cycle of 45/55
鈥?Power Down turns off chip
鈥?Output Enable
鈥?Full CMOS clock swings with 25mA drive
capability at TTL levels
鈥?Advanced, low power CMOS process
鈥?Operating voltages of 3.0 to 5.5 V
Block Diagram
VDD GND
2
S1, S0
PLL,
Divider and
Selection
Circuitry
Input Clock
梅2
Output
Buffer
CLK
Output
Buffer
CLK/2
OE (both outputs)
1
Revision 082500
Printed 11/14/00
Integrated Circuit Systems, Inc. 鈥?25 Race Street鈥?San Jose鈥A鈥?95126鈥?(408)295-9800tel 鈥?www.icst.com
MDS 541 B
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