programmable clock synthesizer. The ICS341 can
reduce system electro-magnetic interference (EMI).
鈩?/div>
software to configure the PLL
and output, the ICS341 contains a One-Time
Programmable (OTP) ROM to allow field
programmability. Programming features include 4
selectable configuration registers.
The device employs Phase-Locked Loop (PLL)
techniques to run from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
The device also has a power-down feature that
tri-states the clock outputs and turns off the PLLs when
the PDTS pin is taken low.
The ICS341 is also available in factory programmed
custom versions for high-volume applications.
Features
鈥?/div>
8-pin SOIC package
鈥?/div>
Highly accurate frequency generation
鈥?/div>
M/N Multiplier PLL: M = 1...2048, N = 1...1024
鈥?/div>
Output clock frequencies up to 200 MHz
鈥?/div>
Four ROM locations for frequency and spread
鈥?/div>
selection
Spread spectrum capability for lower system EMI
鈥?/div>
Center or Down Spread up to 4% total
鈥?/div>
Selectable 32 kHz or 120 kHz modulation
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Input crystal frequency from 5 to 27 MHz
Input clock frequency from 2 to 50 MHz
Operating voltage of 3.3 V
Advanced, low-power CMOS process
For two output clocks, use the ICS342. For three
output clocks, see the ICS343. For more than three
outputs, see the ICS345 or ICS348.
Available in Pb (lead) free packaging
Block Diagram
VDD
S1:0
Crystal or
clock input
X1/ICLK
2
OTP ROM
with PLL
Divider
Values
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
CLK
Crystal
Oscillator
X2
External capacitors are
required with a crystal input.
GND
PDTS (output and PLL)
MDS 341 E
Integrated Circuit Systems, Inc.
鈼?/div>
1
525 Race Street, San Jose, CA 95126
鈼?/div>
Revision 090704
tel (408) 297-1201
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