ICS308
S
ERIAL
P
ROGRAMMABLE
Q
UAD
PLL V
ERSA
C
LOCK
S
YNTHESIZER
Description
The ICS308 is a versatile serially programmable, quad
PLL clock source. The ICS308 can generate any
frequency from 250 kHz to 200 MHz, and up to 6
different output frequencies simultaneously. The
outputs can be reprogrammed on the fly, and will lock to
a new frequency in 10 ms or less. Smooth transitions
(in which the clock duty cycle remains roughly 50%) are
guaranteed if the output divider is not changed.
The device includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS308 default for non-programmed start-up are
buffered reference clock outputs on all clock output
pins.
Features
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Packaged in 20-pin SSOP (QSOP)
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Operating voltage of 3.3 V
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Highly accurate frequency generation
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M/N Multiplier PLL: M = 1..2048, N = 1..1024
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Serially programmable: user determines the output
frequency via a 3-wire interface
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Eliminates need for custom quartz oscillators
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Input crystal frequency of 5 - 27 MHz
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Optional programmable on-chip crystal capacitors
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Output clock frequencies up to 200 MHz
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Reference clock output
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Power down tri-state mode
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Very low jitter
Block Diagram
V DD
3
CLK1
P LL1
CLK2
Divide
Logic
and
Output
Enable
Control
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
STROBE
SCLK
DATA
P LL3
C rystal or
clock input
X 1/IC LK
C rystal
O scillator
X2
GND
2
P D TS
P LL4
P LL2
E xternal capacitors are
required w ith a crystal input.
MDS 308 F
I n t e gra te d C i r c u i t S y s t e m s
鈼?/div>
1
5 25 Race Stre et, San Jo se, CA 9 5126
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Revision 090704
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
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