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Clock outputs from 10 to 133 MHz
Zero input-output delay
Four low skew (<250 ps) outputs
Device-to-device skew <700 ps
Full CMOS outputs with 25 mA output drive
capability at TTL levels
5 V tolerant CLKIN
Tri-state mode for board-level testing
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature range available
Packaged in 8-pin SOIC
Available in Pb (lead ) free package
Block Diagram
VDD
CLKIN
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
GND
MDS 2305 D
I n t e gra te d C i r c u i t S y s te m s
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1
52 5 Ra ce Street, San Jose, CA 9 512 6
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Revision 022505
tel (408 ) 297 -120 1
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