ICS1893 Datasheet

IC型號(hào)：
ICS1893
PDF描述：
3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩
文件大?。?/label>
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PDF頁(yè)數(shù)：
152頁(yè)
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ICS

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Integrated Circuit Systems, Inc.

ICS1893

Document Type:

Data Sheet

Document Stage: Release

3.3-V 10Base-T/100Base-TX Integrated PHYceiver鈩?/div>

General

The ICS1893 is a low-power, physical-layer device (PHY)

that supports the ISO/IEC 10Base-T and 100Base-TX

Carrier-Sense Multiple Access/Collision Detection

(CSMA/CD) Ethernet standards. The ICS1893 architecture

is based on the ICS1892. The ICS1893 supports managed

or unmanaged node, repeater, and switch applications.

The ICS1893 incorporates digital signal processing (DSP) in

its Physical Medium Dependent (PMD) sublayer. As a result,

it can transmit and receive data on unshielded twisted-pair

(UTP) category 5 cables with attenuation in excess of 24 dB

at 100 MHz. With this ICS-patented technology, the

ICS1893 can virtually eliminate errors from killer packets.

The ICS1893 provides a Serial Management Interface for

exchanging command and status information with a Station

Management (STA) entity.

The ICS1893 Media Dependent Interface (MDI) can be

configured to provide either half- or full-duplex operation at

data rates of 10 MHz or 100 MHz. The MDI configuration

can be established manually (with input pins or control

Auto-Negotiation features). When the ICS1893

Auto-Negotiation sublayer is enabled, it exchanges

technology capability data with its remote link partner and

automatically selects the highest-performance operating

mode they have in common.

Features

鈥?/div>

Supports category 5 cables with attenuation in excess of

24 dB at 100 MHz across a temperature range from -5擄to

+85擄C

鈥?/div>

DSP-based baseline wander correction to virtually

eliminate killer packets across temperature range of from

-5擄to +85擄C

鈥?/div>

Low-power, 0.35-micron CMOS (typically 400 mW)

鈥?/div>

Single 3.3-V power supply.

鈥?/div>

Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

鈥?/div>

10Base-T and 100Base-TX IEEE 802.3 compliant

鈥?/div>

Fully integrated, DSP-based PMD includes:

鈥?Adaptive equalization and baseline wander correction

鈥?Transmit wave shaping and stream cipher scrambler

鈥?MLT-3 encoder and NRZ/NRZI encoder

鈥?/div>

Highly configurable design supports:

鈥?Node, repeater, and switch applications

鈥?Managed and unmanaged applications

鈥?10M or 100M half- and full-duplex modes

鈥?Parallel detection

鈥?Auto-negotiation, with Next Page capabilities

鈥?/div>

MAC/Repeater Interface can be configured as:

鈥?10M or 100M Media Independent Interface

鈥?100M Symbol Interface (bypasses the PCS)

鈥?10M 7-wire Serial Interface

鈥?/div>

Small Footprint 64-pin Thin Quad Flat Pack (TQFP)

ICS1893 Block Diagram

100Base-T

10/100 MII or

Alternate

MAC/Repeater

Interface

MUX

PCS

鈥?Frame

鈥?CRS/COL

Detection

鈥?Parallel to Serial

鈥?4B/5B

PMA

鈥?Clock Recovery

鈥?Link Monitor

鈥?Signal Detection

鈥?Error Detection

TP_PMD

鈥?MLT-3

鈥?Stream Cipher

鈥?Adaptive Equalizer

鈥?Baseline Wander

Correction

Integrated

Switch

10Base-T

MII

Extended

Set

Low-Jitter

Clock

Synthesizer

Clock

Power

Twisted-

Pair

Interface to

Magnetics

Modules and

RJ45

Connector

MII Serial

Management

Interface

Configuration

and Status

Auto-

Negotiation

LEDs and PHY

Address

ICS1893 Rev C 6/6/00

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

June, 2000

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