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ICS10001B21 Datasheet

  • ICS10001B21

  • FEMTOCLOCKS-TM DUAL VCXO VIDEO PLL

  • 21頁

  • ICS

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PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS810001-21
F
EMTO
C
LOCKS
鈩?D
UAL
VCXO V
IDEO
PLL
F
EATURES
鈥?/div>
Accepts various HD and SD references including hsync,
transport and pixel clock rates
鈥?/div>
Outputs HD and SD pixel rates
鈥?/div>
One LVCMOS/LVTTL PLL clock output
鈥?/div>
Two selectable LVCMOS/LVTTL input clocks
鈥?/div>
LVCMOS input select lines
鈥?/div>
VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking
鈥?/div>
FemtoClock frequency multiplier provides low jitter, high
frequency output
鈥?/div>
FemtoClock range: 560MHz - 700MHz
鈥?/div>
RMS phase jitter @148.3516484MHz, using a
26.973027MHz crystal (12kHz - 20MHz): 0.81ps (typical)
鈥?/div>
3.3V supply voltage
鈥?/div>
0擄C to 70擄C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS810001-21 is a member of the
HiperClockS鈩?family of high performance clock
HiPerClockS鈩?/div>
solutions from ICS. The ICS810001-21 is a PLL
based synchronous clock generator that is
optimized for digital video clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation, and to support the complex
PLL multiplication ratios needed for video rate conversion.
The second stage is a FemtoClock frequency multiplier that
provides the low jitter, high frequency video output clock.
IC
S
Preset multiplication ratios are selected from internal lookup
tables using device input selection pins. The multiplication ra-
tios are optimized to support most common video rates used in
professional video system applications. The VCXO requires
the use of an external, inexpensive pullable crystal. Two crys-
tal connections are provided (pin selectable) so that both 60
and 59.94 base frame rates can be supported. The VCXO re-
quires external passive loop filter components which are used
to set the PLL loop bandwidth and damping characteristics.
O
UTPUT
R
ATES
S
UPPORTED
:
Frequency (MHz)
27MHz
26.973027MHz
74.25MHz
74.17582418MHz
148.5MHz
148.3516484MHz
36MHz
Application
MPEG Transpor t, ITU-R601, CCIR 656
P
IN
A
SSIGNMENT
XTAL_OUT0
XTAL_OUT1
XTAL_SEL
XTAL_IN0
XTAL_IN1
GND
V
DDX
V
DD
27MHz x 1000/1001
SMPTE 292M/60
SMPTE 292M/59.94
SMPTE 292M/60, 1080P
SMPTE 292M/59.94, 1080P
SMPTE 259M Level 鈥淒鈥?/div>
LF1
LF0
ISET
V
DD
nBP0
GND
CLK_SEL
CLK1
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
V
DD
CLK0
MR
V0
MF
V1
V2
V3
N0
N1
nBP1
OE
GND
Q
V
DDO
V
DDA
ICS810001-21
E
XAMPLE
F
REQUENCY
C
ONVERSIONS
:
All nine combinations from / to:
27MHz
74.175MHz
74.25MHz
NTSC or PAL hsync to 27MHz
NTSC or PAL hsync to 4xFsc
32-Lead VFQFN
5mm x 5mm x 0.95 package body
K Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
810001BK-21
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 12, 2005

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