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ICS002BI72L Datasheet

  • ICS002BI72L

  • FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENU...

  • 18頁

  • IDT

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FEMTOCLOCKS鈩?VCXO BASED WCDMA
CLOCK GENERATOR/JITTER ATTENUATOR
ICS843002I-72
G
ENERAL
D
ESCRIPTION
The ICS843002I-72 is a member of the
HiperClockS鈩?family of high performance clock
HiPerClockS鈩?/div>
solutions from IDT. The ICS843002I-72 is a
PLL based synchronous clock generator that is
optimized for WCDMA channel card applications
where jitter attenuation and frequency translation is needed.
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage uses a VCXO which is optimized
to provide reference clock jitter attenuation and to be jitter
tolerant, and to provide a stable reference clock for the second
PLL stage. The second PLL stage provides additional frequency
multiplication (x32), and it maintains low output jitter by using a
low phase noise FemtoClock鈩?VCO. The device performance
and the PLL multiplication ratios are optimized to support
WCDMA applications. The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the
PLL loop bandwidth and damping characteristics for the given
application.
F
EATURES
鈥?/div>
Two differential LVPECL outputs
鈥?/div>
CLK input accepts the following input levels:
LVCMOS or LVTTL levels
鈥?/div>
Output frequency: 122.88MHz (typical)
鈥?/div>
FemtoClock VCO frequency range: 490MHz - 680MHz
鈥?/div>
RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal
(1.875MHz to 10MHz): 0.49ps (typical)
鈥?/div>
Deterministic jitter: 30fs (typical)
鈥?/div>
Random jitter, RMS: 2.2ps (typical)
鈥?/div>
Full 3.3V or mixed 3.3V core/2.5V output supply voltage
鈥?/div>
-40擄C to 85擄C ambient operating temperature
鈥?/div>
Available in lead-free (RoHS 6) package
IC
S
The ICS843002I-72 can accept a single-ended input. LOCK_DT
reports the lock status of VCXO PLL loop. If the reference clock
input is lost, it will set LOCK_DT to logic LOW.
Typical ICS843002I-72 configuration in WCDMA Systems:
鈥?/div>
19.2MHz pullable crystal
鈥?/div>
Input Reference clock frequency: 3.84MHz
鈥?/div>
Output clock frequency: 122.88MHz
P
IN
A
SSIGNMENT
XTAL_OUT
XTAL_IN
V
CC
V
CC
V
CC
V
EE
V
EE
nc
32 31 30 29 28 27 26 25
LF1
LF0
ISET
V
CC
V
CC
V
EE
V
EE
CLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q0
V
CCA
V
CCO
nOE
nQ0
V
EE
V
EE
V
EE
24
23
22
21
20
19
18
17
LOCK_DT
V
EE
V
CC
V
CCO
V
CCO
nQ1
Q1
V
EE
ICS843002I-72
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
IDT
鈩?/div>
/ ICS
鈩?/div>
WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
1
ICS843002BKI-72 REV. A NOVEMBER 21, 2007

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