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ICD2093SC-1 Datasheet

  • ICD2093SC-1

  • CPU SYSTEM CLOCK GENERATOR|CMOS|SOP|24PIN|PLASTIC

  • 164.48KB

  • 10頁

  • ETC

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1I CD20 93
fax id: 3508
ICD2093
鈥淪uper Buffer鈥?Clock Generator
Features
鈥?Selectable CPU clock provides eight 2X or 1X outputs
which handle all 486 processor clocking requirements
鈥?Less than 250 ps total skew between Hi-Drive (48 mA),
Hi-Load (50 pF) CPU clock outputs
鈥?Four fixed outputs:
14.31818 MHz (2), 16 MHz, and 24 or 32 MHz handle all
other system clocking requirements
鈥?CPU clock frequency range:
10 MHz to 100 MHz with 50% duty cycle
鈥?Optional power-down mode
鈥?Three-state oscillator control disables outputs for test
purposes
鈥?Phase-locked loop oscillator input derived from single
14.31818 MHz crystal
鈥?Sophisticated internal loop-filter requires no external
components
鈥?5V operation
鈥?Low-power, high-speed CMOS technology
鈥?Available in 24-pin SOIC package configuration
Functional Description
Today鈥檚 high-end personal computers require a CPU system
clock which exhibits a large drive capability (high fanout) with-
out degradation in rise and fall times. The classical solution
has been to distribute and buffer this clock. The ICD2093
alleviates this problem by providing eight 1X or 2X Clock out-
puts with extremely low skew between outputs.
The ICD2093 also supplies other clocks required in a high-per-
formance system: the system I/O and bus clocks.
The ICD2093 consists of one crystal controlled oscillator, two
phase-locked loops, and twelve different outputs in a single
package.
Block Diagram
CPUA
CPUB
SKEW ADJUST
梅4
CPUCLK
PLL
S2
S1
S0
CPUC
CPUD
CPUE
CPUF
CPUG
CPUH
Configuration
option:
梅1
or
梅2
outputs)
梅6
XTALIN
XTALOUT
(INPUT FROM
14.31818 MHz
AL)
CRYST
OSCILLATOR
SYSCLK
PLL
96 MHz
梅4
梅3
2:1
MUX
16 MHz
SYSCLK
(24 or 32 MHz)
(Configuration option)
SYSBUS_A
SYSBUS_B
ICD2093-1
GND (3)
V
DD
(2)
AV
DD
SHUTDOWN
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
June 1994

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