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ICD2025-S1 Datasheet

  • ICD2025-S1

  • CPU SYSTEM CLOCK GENERATOR|CMOS|SOP|16PIN|PLASTIC

  • 8頁(yè)

  • ETC

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1I CD20 25
fax id: 3505
ICD2025
Motherboard Clock Generator
Features
鈥?Three independent clock outputs: separate CPUCLK,
SYSCLK and Buffered Reference Clock
鈥?Ideally suited for 386/486 motherboard applications
鈥?/div>
Phase-locked loop output range of 1.843 MHz
鈭?/div>
100 MHz
鈥?Phase-locked loop oscillator input derived from single
14.31818 MHz crystal
鈥?Sophisticated internal loop-filter requires no external
components or manufacturing tweaks as commonly re-
quired with external filters
鈥?Three-state oscillator control disables outputs for test
purposes
鈥?5V operation
鈥?Low-power, high-speed CMOS technology
鈥?Available in 16-pin SOIC package
Functional Description
A modern personal computer motherboard often requires
many different crystal can oscillators. The System Logic fam-
ily of frequency synthesis parts from Cypress/IC Designs re-
places the large number of oscillators required to build such
multi-function motherboards. These parts synthesize all the
required frequencies in a single monolithic device, thus lower-
ing manufacturing costs and significantly reducing the printed
circuit borad space required.
The ICD2025 is a low-cost approach to the generation of the
3 necessary clocks required by any PC motherboard.
Logic Block Diagram
SYSBUS
14.318 MHz
梅n
7
ROM
7
C0
C1
C2
C3
S0
S1
S2
GND
V
DD
AV
DD
Phase
Detector
Charge
Pump
Internal Loop Filter
梅m
VCO
CPUCLK
f
REF
/
XTALIN
XTALOUT
Phase鈥揕ockedLoop
Oscillator #1
PLL #2
SYSCLK
OE
ICD2025鈥?
Pin Configuration
SOIC
Top View
SYSBUS
SYSCLK
OE
GND
f
REF
/XTALIN
XTALOUT
C0
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AV
DD
CPUCLK
C3
V
DD
S2
C2
C1
S1
ICD2025鈥?
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
August 1994 鈥?Revised April 1995

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