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IBM25CPC700CB3B66 Datasheet

  • IBM25CPC700CB3B66

  • Peripheral (Multifunction) Controller

  • 20頁(yè)

  • ETC

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.
CPC700 Memory Controller and PCI Bridge
Features
鈥?PowerPC 60x/7xx bus.
鈥?66.66 MHz (IBM25CPC700BB3B66).
鈥?83.33 MHz (IBM25CPC700BB3B83).
鈥?Synchronous DRAM interface operates at the
processor bus speed with support for ECC.
鈥?PCI Revision 2.1 Compliant Interface.
鈥?ROM/SRAM/External peripheral controller.
鈥?Interrupt Controller supports interrupts from a
variety of sources.
鈥?Programmable Timers.
鈥?Two 2-wire, 8-bit, 16550 compatible UARTs.
鈥?Two independent IIC interfaces.
鈥?Byte swapping supported for bi-endian opera-
tion.
鈥?Internal PCI Bus Arbiter for PCI bus speeds up
to 33.33 MHz (may be disabled for use with an
external arbiter).
鈥?32-bit PCI bus operates at frequencies from
25MHz to 66.66 Mhz.
鈥?Uses standard type 0 PCI con鏗乬uration register
map essential to making it appear like a device
but does not preclude it from being a host.
鈥?Supports independent primary and secondary
resource management mapping. This feature
enables the CPC700 to effectively isolate local
processing resources from host side memory
and I/O allocations. Through the use of three
independent translation decodes, the PowerPC
operating environment access to PCI is man-
aged solely by the PowerPC.
鈥?Dual address capabilities enhance the
CPC700鈥檚 capabilities by allowing it to manage,
control, or test beyond 4GB limitations.
鈥?Support for shared memory is locally mapped to
the processor鈥檚 ROM or SDRAM through PCI
standard Base Address Registers. Two Memory
I/O BARs are available for requesting host
memory or I/O resources and managing PCI to
PowerPC access.
鈥?Provides a special interface enabling the
CPC700 to generate any PCI command, includ-
ing Type 1 con鏗乬uration cycles.
鈥?Fully buffers PCI writes and supports PCI read
pre-fetching from local memory.
鈥?Hardware enforces cache coherency.
鈥?Implemented in CMOS5SE.
cpc700_ds2.fm
05/04/00
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