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IBM13Q32734BCA-10Y Datasheet

  • IBM13Q32734BCA-10Y

  • x72 SDRAM Module

  • 15頁

  • ETC

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Discontinued (4/1/00 - last order; 7/31/00 - last ship)
.
IBM13Q32734BCA
32M x 72 Registered SDRAM Module
Features
鈥?200-Pin JEDEC Standard, Registered 8-Byte
Dual In-line Memory Module
鈥?32M x 72 Synchronous DRAM DIMM
鈥?Performance:
CAS Latency = 2*
f
CK
t
CK2
t
AC2
Clock Frequency
Clock Cycle
Clock Access Time
-10
66
15
11.3
Units
MHz
ns
ns
鈥?Automatic and controlled Precharge Commands
鈥?Programmable Operation:
-SDRAM CAS Latency: 2
-Burst Type: Sequential or Interleave
-Burst Length: 2
-Operation: Burst Read and Write or Multiple
Burst Read with Single Write
鈥?Suspend Mode and Power Down Mode
鈥?12/10/2 Addressing (Row/Column/Bank)
鈥?4096 Refresh cycles distributed across 64ms
鈥?Parallel Presence Detect
鈥?Card size: 6.05" x 1.50" x 0.320"
鈥?Gold contacts
鈥?SDRAM
S
in TSOJ Type II, 2-High, Stacked
Package
* SDRAM CAS latency = 2; DIMM CAS Latency = 3
鈥?Inputs and outputs are LVTTL (3.3V) compatible
鈥?Single 3.3V to 3.6V Power Supply
鈥?Single Pulsed RAS interface
鈥?Fully Synchronous to positive Clock Edge
鈥?Data Mask control
鈥?Auto Refresh (CBR) and Self Refresh
Description
IBM13Q32734BCA is a registered 200-pin Synchro-
nous DRAM Dual In-line Memory Module (DIMM)
which is organized as a 32Mx72 high-speed mem-
ory array. The DIMM uses eighteen x4 SDRAMs in
400mil TSOJ II stacked packages. The DIMM
achieves high speed data transfer rates of up to
66MHz by employing a prefetch/pipeline hybrid
architecture that supports the JEDEC 1N rule while
allowing very low burst power.
The DIMM is intended to comply with all non-
optional JEDEC standards set for the 200-pin regis-
tered SDRAM DIMMs.
All control and address signals are synchronized
with the positive edge of an externally supplied
clock. They are latched in an on-DIMM pipeline
register and presented to the SDRAMs on the fol-
lowing clock.
Prior to any Access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the DIMM by address
inputs A0-A13 using the Mode Register Set cycle.
The DIMM uses parallel presence detects imple-
mented according to the JEDEC standard.
All IBM 200-pin DIMMs provide a high performance,
flexible 8-byte interface in a 6.05鈥?long high-perfor-
mance footprint. Related products include both EDO
DRAM and SDRAM unbuffered DIMMs in both non-
parity x64 and ECC-Optimized x72 configurations in
the 168 pin form factor.
04K8918.C75665B
6/99
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 15

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