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IBM0418A81QLAA-5 Datasheet

  • IBM0418A81QLAA-5

  • x18 Fast Synchronous SRAM

  • 25頁

  • ETC

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IBM0418A81QLAA IBM0436A81QLAA
IBM0418A41QLAA IBM0436A41QLAA
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
鈥?8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
鈥?0.25 Micron CMOS technology
鈥?Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
鈥?Single Differential Extended HSTL Clock
鈥?+3.3V Power Supply, Ground, 1.5V V
DDQ
, and
0.75V V
REF
鈥?HSTL Inputs and Output levels
鈥?Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
鈥?Registered Outputs
鈥?Common I/O
鈥?Asynchronous Output Enable a
鈥?Synchronous Power Down Inputs
鈥?Boundary Scan using limited set of JTAG
1149.1 functions
鈥?Byte Write Capability and Global Write Enable
鈥?7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The 4Mb and 8Mb SRAMs鈥擨BM0436A41QLAA,
IBM0418A41QLAA, IBM0418A81QLAA, and
IBM0436A81QLAA鈥攁re Synchronous Pipeline
Mode, high-performance CMOS Static Random
Access Memories that are versatile, have wide I/O,
and can achieve 3ns cycle times. Differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the next rising edge of the K clock. An inter-
nal Write buffer allows write data to follow one cycle
after addresses and controls. The chip is operated
with a single +3.3V power supply and is compatible
with HSTL I/O interfaces.
trrh3316.06
12/00
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 25

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