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I960 Datasheet

  • I960

  • i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS

  • 70頁(yè)

  • INTEL   INTEL

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ADVANCE INFORMATION
i960
廬
RP/RD I/O PROCESSOR AT 3.3 VOLTS
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鈥?/div>
鈥?/div>
鈥?/div>
33 MHz, 3.3 Volt Version (80960RP 33/3.3)
66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core
Complies with PCI Local Bus Specification Revision 2.1
5 Volt PCI Signalling Environment
s
DMA Controller
s
High Performance 80960JF Core
s
s
s
s
鈥?Sustained One Instruction/Clock
Execution
鈥?4 Kbyte Two-Way Set-Associative
Instruction Cache
鈥?2 Kbyte Direct-Mapped Data Cache
鈥?Sixteen 32-Bit Global Registers
鈥?Sixteen 32-Bit Local Registers
鈥?Programmable Bus Widths:
8-, 16-, 32-Bit
鈥?1 Kbyte Internal Data RAM
鈥?Local Register Cache
(Eight Available Stack Frames)
鈥?Two 32-Bit On-Chip Timer Units
PCI-to-PCI Bridge Unit
鈥?Primary and Secondary PCI Interfaces
鈥?Two 64-Byte Posting Buffers
鈥?Delayed and Posted Transaction
Support
鈥?Forwards Memory, I/O, Configuration
Commands from PCI Bus to PCI Bus
Two Address Translation Units
鈥?Connects Local Bus to PCI Buses
鈥?Inbound/Outbound Address Translation
Support
鈥?Direct Outbound Addressing Support
Messaging Unit
鈥?Four Message Registers
鈥?Two Doorbell Registers
鈥?Four Circular Queues
鈥?1004 Index Registers
Memory Controller
鈥?256 Mbytes of 32- or 36-Bit DRAM
鈥?Interleaved or Non-Interleaved DRAM
鈥?Fast Page-Mode DRAM Support
鈥?Extended Data Out and Burst
鈥?Extended Data Out DRAM Support
鈥?Two Independent Banks for SRAM / ROM
/ Flash (16 Mbytes/Bank; 8- or 32-Bit)
s
s
s
s
Three Independent Channels
PCI Memory Controller Interface
32-Bit Local Bus Addressing
64-Bit PCI Bus Addressing
Independent Interface to Primary and
Secondary PCI Buses
鈥?132 Mbyte/sec Burst Transfers to PCI
and Local Buses
鈥?Direct Addressing to and from PCI
Buses
鈥?Unaligned Transfers Supported in
Hardware
鈥?Two Channels Dedicated to Primary
PCI Bus
鈥?One Channel Dedicated to Secondary
PCI Bus
I/O APIC Bus Interface Unit
鈥?Multiprocessor Interrupt Management
for Intel Architecture CPUs
(Pentium
廬
and Pentium
廬
Pro
Processors)
鈥?Dynamic Interrupt Distribution
鈥?Multiple I/O Subsystem Support
I
2
C Bus Interface Unit
鈥?Serial Bus
鈥?Master/Slave Capabilities
鈥?System Management Functions
Secondary PCI Arbitration Unit
鈥?Supports Six Secondary PCI Devices
鈥?Multi-priority Arbitration Algorithm
鈥?External Arbitration Support Mode
Private PCI Device Support
鈥?352 Ball-Grid Array (HL-PBGA)
鈥?/div>
鈥?/div>
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鈥?/div>
鈥?/div>
s
SuperBGA* Package
漏 INTEL CORPORATION, 1997
September, 1997
Order Number:
273001-002

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