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HYS72V64200GR-8B Datasheet

  • HYS72V64200GR-8B

  • x72 SDRAM Module

  • 25頁

  • ETC

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HYS 72Vx2x0GR
Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
64 MB, 128 MB, 256 MB, 512 MB & 1 GB Densities
鈥?168-pin JEDEC Standard, Registered 8 Byte
Dual-In-Line SDRAM Module
for PC and Server main memory applications
鈥?One bank 8M
脳
72, 16M
脳
72, 32M
脳
72 and
64M
脳
72 organization
two bank 32M
脳
72 & 128M
脳
72 organization
鈥?Optimized for ECC applications with very low
input capacitances
鈥?Programmed Latencies:
Product Speed
-8
-8A
-8B
PC100
PC100
PC100
CL
2
3
3
t
RCD
t
RP
鈥?Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?All inputs and outputs are LVTTL compatible
鈥?Serial Presence Detect with E
2
PROM
鈥?Utilizes 64M & 256M SDRAMs in TSOPII-54
packages with registers and PLL.
The two bank module uses stacked TSOP54
packages.
鈥?Card Size: 133.35 mm
脳
38.1 mm/
43.18 mm
脳
4,00/6.50 mm with Gold contact
pads
鈥?This specification follows INTEL鈥檚 鈥淧C
SDRAM Registered DIMM Specification鈥?/div>
Rev. 1.2
2
2
2
2
2
3
鈥?Single + 3.3 V (鹵 0.3 V) power supply
鈥?Performance:
-8
PC100
f
CK
t
CK
t
AC
-8A
PC100
100
10
6
-8B
PC100
100
10
6
Unit
Clock Frequency (max.)
Clock Cycle Time (min.)
Clock Access Time (min.)
100
10
6
MHz
ns
ns
The HYS 72Vx2x0GR family are industry standard 168-pin 8-byte Dual in-line Memory Modules
(DIMMs) which are organized as 8M
脳
72, 16M
脳
72, 32M
脳
72, 64M
脳
72 & 128M
脳
72 high speed
memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. All control
and address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock
inputs. The 256 MB module is available as one bank and two bank module version. Use of an on-
board register reduces capacitive loading on the input signals but are delayed by one cycle in
arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs
use a serial presence detects scheme implemented via a serial E
2
PROM using the 2-pin I
2
C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte
interface in a 133.35 mm long footprint.
Data Book
1
11.99

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