HYS 72Dxx0xxGR-7/8-A
Registered DDR-I SDRAM-Modules
2.5 V 184-pin Registered DDR-I SDRAM Modules
256MB, 512MB &1GByte Modules
PC1600 & PC2100
鈥?184-pin Registered 8-Byte Dual-In-Line
DDR-I SDRAM Module for PC and Server
main memory applications
鈥?One bank 32M
脳
72, 64M x 72, and two bank
64M x 72, 128M
脳
72 organization
鈥?JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM) with a
single + 2.5 V (
鹵
0.2 V) power supply
鈥?Built with 256Mbit DDR-I SDRAMs in 66-
Lead TSOPII package
鈥?Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
鈥?Performance:
鈥?Auto Refresh (CBR) and Self Refresh
鈥?All inputs and outputs SSTL_2 compatible
鈥?Re-drive for all input signals using register
and PLL devices.
鈥?Serial Presence Detect with E
2
PROM
鈥?Jedec standard MO-206 form factor:
133.35 mm (nom.)
脳
43.18 mm (nom.)
脳
4.00
mm (max.)
(6,80 mm max. with stacked components)
鈥?Jedec standard reference layout:
Raw Cards A, B and C
鈥?Gold plated contacts
-7
Component Speed Grade
Module Speed Grade
f
CK
f
CK
-8
PC1600
125
100
Unit
DDR266A DDR200
PC2100
143
133
MHz
MHz
Clock Frequency (max.) @ CL = 2.5
Clock Frequency (max.) @ CL = 2
Description
The HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs)
organized as 32M
脳
72 (256MB), 64M
脳
72 (512MB) and 128M
脳
72 (1GB). The memory array is
designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock
distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM
timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E
2
PROM device using the 2-pin I
2
C protocol. The first 128 bytes
are programmed with configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
1
2002-05-08 (revision 1.0)