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Gflx Standard HyperPHY
OVERVIEW
HyperPHY is an LSI Logic CoreWare transceiver technology family
designed for broadband and networking applications for extremely high band-
width CMOS ASICs.
TM
廬
FEATURES
鈥?Data rates from 528 Mbps to 800
Mbps
鈥?Supports SPI-4.2 and SFI-4 standards
鈥?8-bit parallel word with associated
clock
鈥?Up to 128 full duplex channels
allowed on a single ASIC
鈥?LVDS buffers with on-chip termination
resistors
鈥?Physically separate serializer and
de-serializer cores
鈥?Typical 55 mW per full duplex chan-
nel at 622 Mbps
鈥?Allows at-speed built-in-self-test of full
transmit and receive/clock recovery
functions
鈥?Able to receive data reliably even
with long sequences of data without
transitions
鈥?Receiver channel-to-channel de-skew
鈥?Produced in LSI Logic Gflx technolo-
gy (0.13 micron CMOS)
鈥?1.2V supply
HyperPHY transceiver technology includes a full clock recovery mechanism
that permits the recovery of clock and data from a data stream alone.
Communication on HyperPHY channels is possible over a variety of physical
media, including copper cable and printed circuit board traces with high speed
backplane connectors
G
flx
T M
S T A N D A R D H Y P E R P H Y D E S C R I P T I O N
Gflx
TM
Standard HyperPHY represents the fourth generation of a continuing
transceiver technology family. The HyperPHY methodology allows for the con-
struction of transceiver architectures in an ASIC methodology.
The cores consist of a serializer, a de-serializer with clock and data recov-
ery, and a low-jitter PLL. These cores, shown in Figure 1 as TX, RX and PLL,
respectively, are combined into sub-systems per customer specifications. Figure
1 shows a generic full duplex subsystem, with 32 independent receive channels
and 32 independent transmit channels, all serviced by a single PLL.
RX Channel 32
RX Channel 2
RX Channel 1
Receive Data Word
20
P
S
Clock
and
Data
Recovery
Serial
LVDS
Receiver
TX Channel 32
TX Channel 2
TX Channel 1
Transmit Data Word
20
P
S
Serial
LVDS
Driver
High Speed
Serial TX Data
High Speed
Serial RX Data
Receive Data Word Clock
(8 bit word)
Control
BENEFITS
鈥?Modular building blocks allow for
flexible architectures with an ASIC-
friendly design approach
鈥?Separate serializer and de-serializer
cores allow for data flow architectures
鈥?Supports OC-12/STM-4 data rate
with up to two levels of forward error
correction
Transmit Data Word Clock
(8 bit word)
Control
PLL Clock To All Channels
PLL
Reference Clock
Figure 1: Block diagram of ASIC subsystem using Gflx Standard HyperPHY
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