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HYMD2646468 Datasheet

  • HYMD2646468

  • 64Mx64|2.5V|K/H/L|x16|DDR SDRAM - Unbuffered DIMM 512MB

  • 16頁

  • ETC

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64Mx64 bits
Unbuffered DDR SDRAM DIMM
HYMD264646(L)8-K/H/L
DESCRIPTION
Hynix HYMD264646(L)8-K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Mem-
ory Modules (DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix HYMD264646(L)8-K/H/L
series consists of sixteen 32Mx8 DDR SDRAM in 400mil TSOPII packages on a184pin glass-epoxy substrate. Hynix
HYMD-264646(L)8-K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry
standard. It is suitable for easy interchange and addition.
Hynix HYMD264646(L)8-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper-
ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD264646(L)8-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
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512MB (64M x 64) Unbuffered DDR DIMM based on
32Mx8 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
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Data inputs on DQS centers when write (centered
DQ)
Data strobes synchronized with output data for read
and input data for write
Programmable CAS Latency 2 / 2.5 / 3 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
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ORDERING INFORMATION
Part No.
HYMD264646(L)8-K
HYMD264646(L)8-H
HYMD264646(L)8-L
V
DD
=2.5V
V
DDQ
=2.5V
Power Supply
Clock Frequency
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
Interface
Form Factor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
* JEDEC Defined Specifications compliant
SSTL_2
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.8/Oct. 02
1

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