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HYMD1167258 Datasheet

  • HYMD1167258

  • 16Mx72|2.5V|H/L|x9|DDR SDRAM - Unbuffered DIMM 128MB

  • 16頁

  • ETC

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HYMD1167258-H/L
16Mx72 Unbuffered DDR SDRAM DIMM
PRELIMINARY
DESCRIPTION
Hynix HYMD1167258-H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Mod-
ules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD1167258-H/L series consists of
nine 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD1167258-H/L
series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for
easy interchange and addition.
Hynix HYMD1167258-H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations
referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD1167258-H/L series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
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128MB (16M x 72) Unbuffered DDR DIMM based on
16Mx8 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory module
(DIMM)
Error Check Correction (ECC) Capability
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
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Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
Data inputs on DQS centers when write (centered
DQ)
Data strobes synchronized with output data for read
and input data for write
Programmable CAS Latency 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD1167258-H
HYMD1167258-L
Power Suppy
V
DD
=2.5V
V
DDQ
=2.5V
Clock Frequency
133MHz (*DDR266B)
100MHz (*DDR200)
Interface
SSTL_2
Form Factor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.1.3/Apr.01

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