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HYM7V65401BTQG Datasheet

  • HYM7V65401BTQG

  • 8Mx64|3.3V|P/S|x8|SDR SDRAM - SO DIMM 64MB

  • 14頁

  • ETC

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4Mx64 bits
PC100 SDRAM SO DIMM
based on 4Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM7V65401B Q-Series
DESCRIPTION
The Hynix HYM7V65401B Q-Series are 4Mx64bits Synchronous DRAM Modules. The modules are composed of four
4Mx16bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP package
on a 144pin glass-epoxy printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the
PCB.
The HYM7V65401B Q-Series are Small Outline Dual In-line Memory Modules suitable for easy interchange and addition
of 32Mbytes memory. The HYM7V65401B Q-Series are offering fully synchronous operation referenced to a positive
edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are
internally pipelined to achieve very high bandwidth.
FEATURES
鈥?/div>
PC100MHz support
鈥?/div>
144pin SDRAM SO DIMM
鈥?/div>
Serial Presence Detect with EEPROM
鈥?/div>
1.00鈥?(25.40mm) Height PCB with Double Sided
components
鈥?/div>
Single 3.3
鹵
0.3V power supply
鈥?/div>
All devices pins are compatible with LVTTL interface
鈥?/div>
Data mask function by DQM
鈥?/div>
SDRAM internal banks : four banks
鈥?/div>
Module bank : one physical bank
鈥?/div>
Auto refresh and self refresh
鈥?/div>
4096 refresh cycles / 64ms
鈥?/div>
Programmable Burst Length and Burst Type
-. 1, 2, 4, 8, or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
鈥?/div>
Programmable /CAS Latency
-. 2, 3 Clocks
ORDERING INFORMATION
PART NO.
HYM7V65401BTQG-8
HYM7V65401BTQG-10P
HYM7V65401BTQG-10S
HYM7V65401BLTQG-8
HYM7V65401BLTQG-10P
HYM7V65401BLTQG-10S
MAX.
FREQUENCY
125MHz
100MHz
100MHz
125MHz
100MHz
100MHz
4 Banks
4K
Low Power
Normal
TSOP-II
Gold
INTERNAL
BANK
REF.
POWER
SDRAM
PACKAGE
PLATING
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not
assume any responsibility for use of circuits described. No patent licenses are implied.
1
Rev. 1.2/Dec. 01

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