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HYM72V12C736BLS4 Datasheet

  • HYM72V12C736BLS4

  • 128Mx72|3.3V|K/H|x36|SDR SDRAM - Registered DIMM 1GB

  • 15頁(yè)

  • ETC

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128Mx72 bits
PC133 SDRAM Registered DIMM
with PLL, based on 64Mx4 SDRAM with LVTTL, 4 banks & 8K
Refresh
HYM72V12C736B(L)S4 Series
DESCRIPTION
The HYM72V12C736B(L)S4 Series are 128Mx72bits ECC Synchronous DRAM Modules. The modules are composed
of thirty six 64Mx4bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II stack package, one 2Kbit EEPROM in
8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capac-
itors per each SDRAM are mounted on the PCB.
The HYM72V12C736B(L)S4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of
1Gbytes memory. The HYM72V12C736B(L)S4 Series are fully synchronous operation referenced to the positive edge
of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are inter-
nally pipelined to achieve very high bandwidth.
鈥?/div>
PC133MHz
FEATURES
support
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鈥?/div>
鈥?/div>
168pin SDRAM Registered DIMM
Serial Presence Detect with EEPROM
1.70鈥?(43.18mm) Height PCB with double sided
components
Single 3.3鹵0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
鈥?/div>
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All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
鈥?/div>
Programmable CAS Latency ; 2, 3 Clocks
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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SDRAM internal banks : four banks
Module bank : two physical banks
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HYM72V12C736BS4-K
HYM72V12C736BS4-H
HYM72V12C736BLS4-K
HYM72V12C736BLS4-H
133MHz
4 Banks
8K
Low Power
Clock
Frequency
Internal
Bank
Ref.
Power
Normal
SDRAM
Package
Plating
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4/Dec. 2002
1

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