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HYB39S64160AT-7 Datasheet

  • HYB39S64160AT-7

  • x16 SDRAM

  • 18頁

  • ETC

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HYB39S64160A/BT-5.5/-6/-7
64MBit Synchronous DRAM
4M x 16 MBit Synchronous DRAM
for High Speed Graphics Applications
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High Performance:
-5.5
fCKmax @ CL=3
tCK3
tAC3
fCKmax @ CL=2
tCK2
tAC2
183
5.5
4.5
133
7.5
5.4
-6
166
6
5
125
8
6
-7
143
7
5.5
115
9
6
Units
MHz
ns
ns
MHz
ns
ns
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full page(optional) for sequencial wrap
around
Multiple Burst Read with Single Write
Operation
Automatic
Command
and
Controlled
Precharge
Data Mask for Read / Write control
Dual Data Mask for byte control
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles / 64 ms
Latency 2 @ 133 MHz
Latency 3 @ 183 MHz
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPII-54 400mil width
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Fully Synchronous to Positive Clock Edge
0 to 70
擄C
operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency : 2, 3
Programmable Wrap Sequence : Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
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The HYB39S64160A/BT-5.5/-6/-7 are high speed dual bank Synchronous DRAM鈥檚 based on
INFINEON 0.25碌m (A1-die) and 0.2碌m (B-die) process and organized as 4 banks x 1Mb x 16.
These synchronous devices achieve high speed data transfer rates up to 183 MHz by employing a
chip architecture that prefetches multiple bits and then synchronizes the output data to a system
clock. The chip is fabricated with INFINEON鈥?advanced 16MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 183
MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
INFINEON Technologies
1
7.99

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