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HY64LD16162M Series

Document Title

1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

Revision history

Revision No. History

1.0

1.1

Initial

Revised

- Change Pin Connection

- Improve tOE from 45ns to 30ns

- Correct State Diagram

1.2

Revised

- Correct Package Dimension

- Change Absolute Maximum Ratings

1.3

Revised

- DC Electrical Characteristics ( I

DPD

,I

CC1

)

- State Diagram

- Power Up Sequence

- Deep Power Down Sequence

- Read/Write Cycle Note

1.4

Revised

- DC Electrical Characteristics ( ICC1: 3mA - > 5mA)

1.5

Revised

- Improve Standby Current I

SB1

from 100uA to 80uA

- Power Up Sequence

Dec. 20. 鈥?01

Final

Nov. 14. 鈥?01

Preliminary

Oct. 07. 鈥?01

Preliminary

Jul.18. 鈥?01

Preliminary

Draft Date

Jan. 04. 鈥?01

Jul. 03. 鈥?01

Remark

Preliminary

Preliminary

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume

1

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